Current emerging memory read operations convert a resistance state stored in a bit-cell into one or more current signals on a cell current branch. A conventional current sense amplifier includes two-stage amplification. The first stage includes two branches, a reference branch and cell branch. The reference branch generates a reference current (Iref) and a reference voltage (Vref) input for a sense amplifier. The cell branch generates a cell current (Icell) and includes an adjustable resistor RRAM. The current difference between the cell current and the reference current generates a voltage signal (Vdi) second input of the sense amplifier. If Vdi is greater than Vref, a logic “1” is read during the read operation. If Vdi is less than Vref, a logic “0” is read during the read operation.
Because Vdi is pulled down from VDD to a final stabilized level for a logic “1”, the conventional current sense amplifier requires a substantial (>10 nanoseconds) stabilization time to settle the current signal to a reference level. After the current signal is settled, the sense amplifier compares Vdi and Vref to generate a logic output. The stabilization time needed in conventional current sense amplifiers prevents read operations from being performed at high-speeds (such as <10 nanoseconds). Further, conventional current sense amplifiers produce a high spike current during a read operation.